Multilayer printed wiring board

ABSTRACT

A multi-layer printed wiring board including a first substrate having an opening and having external terminals positioned to be connected to a package substrate, a second substrate laminated to the first substrate and having external terminals positioned to be connected to a mother board, the second substrate having a metallic layer portion in the opening of the first substrate and non-through holes filled with conductive material and connected to the metallic layer portion, and an IC component having terminals and loaded in the opening of the first substrate such that the terminals of the IC component face an opposite side of the metallic layer portion of the second substrate. The IC chip is accommodated in the opening such that the metallic layer portion and non-through holes of the second substrate irradiate heat generated by the IC chip.

TECHNICAL FIELD

The present invention relates to a multi-layer printed wiring boardloaded with electronic components such as IC chips and more particularlyto a multi-layer printed wiring board which enables the IC chip to bemulti-layered and is not affected by stress and the like.

BACKGROUND ART

Technology which multi-layers an insulation substrate having IVH (innervia hole) structure while equipped with a conductive layer on one sidehas been proposed (for example, Japanese Patent Application Laid-OpenNo. HEI10-13028 and the like). This makes electric connection byconnecting the conductive layer of one insulating base material with thevia hole in the other insulating base material. Its function is exertedby mounting electric components such as IC chip and capacitor on aconductor circuit on an external layer appropriately. As a conventionalart, Japanese Patent Application Laid-Open No. HEI10-13028 has beenknown.

FIG. 24 shows a printed wiring board for loading an IC chip according toa conventional art. FIG. 24(A) shows a plan view, and FIG. 24(B) shows asectional view taken along the line B-B of FIG. 24(A). As shown in FIG.24(B), a substrate 110 constituting a printed wiring board comprises acavity 110 a for accommodating an IC chip 170 and a via hole 118 forconnecting the front face with the rear face. A rectangular bonding pad136 is formed integrally on a land 118 a of the via hole 118. A solderedbump 156 is connected to the rear face of the via hole 118 through aconductor circuit 138. The bonding pad 136 formed integrally with thevia hole land 118 a is projected from an opening 144 of soldered resistlayer 140 so that its front end is exposed outside and wire-bonded witha terminal 171 of the IC chip 170 and wire 172.

Reduced thickness of film and intensified function of a substrate loadedwith the IC chip have been demanded. The reason is that the casing of anelectronic product such as portable phone, camera and personal computerhas been reduced in size and thickness. To be accommodated in thosecasings, all the materials and components need to be thinned whilekeeping their function from dropping. Thus, constructing the IC chip inmulti-layers so that its layers are stacked (in three dimensions) hasbeen considered. According to the technology, an IC chip is loadeddirectly on an IC chip for multi-layer structure, that is, an upper ICchip is mounted on a lower IC chip by die bonding to stack layers. Thelayered IC chips are connected through the wire bonding. As a result,high density and small size can be achieved on the same area.

However, the substrate loaded with the layered IC chips cannot berepaired. Further, because connection is gained by wire bonding afterthe loading, the IC chip or the substrate cannot be inspected until theconnection is gained by wire bonding. Thus, if there is even a singledefect in the IC chip, the loaded substrate itself cannot be used.

Further, because no circuit is formed below the layered circuit orbetween IC chips, wiring cannot be placed around. Thus, with increase inclock number or the like, the wiring length prolongs. Upon a change indesign or change in specification, appropriate formation by loadingneeds to be considered.

The present invention has been achieved to solve the above-describedproblems and an object of the invention is to provide a multi-layerprinted wiring board which is easy to be multi-layered in terms of itsstructure and capable of withstanding changes in specification fordesign or the like.

Further, the board loaded with the IC chip has been demanded to have ahigher wiring density. For this purpose, bonding pads for wire bondingneed to be disposed in high density. However, because shown in FIG.24(A), if the bonding pad 136 is formed integrally with a via hole land118 a, the via hole land 118 a whose external shape is larger than theline width of the bonding pad 136 is disposed, the bonding pads cannotbe disposed in high density.

The present invention has been achieved to solve the above-describedproblem and another object of the invention is to provide a multi-layerprinted wiring board which enables the wiring density of the wirebonding to be intensified.

DISCLOSURE OF THE INVENTION

As a result of research by the inventor, as a multi-layer printed wiringboard loaded with an electronic component such as an IC chip and havingexternal terminals, a structure in which the external terminals aredisposed on both faces thereof has been proposed to solve theabove-described problem.

Because the both faces of the multi-layer printed wiring board have apad for connecting to the external terminal, other printed wiring boardcan be connected to the both faces. For example, with other IC modulemounted through the external terminals on the front face, this printedwiring board can be connected to a printed wiring board through theexternal terminal on the rear face. Freedom in the configuration of theIC module to be mounted increases. Especially, it is preferable todispose an external terminal just under the IC chip. As a consequence,freedom of wire to be drawn increases and further, the IC chip turnsinto a structure which enables the IC chips to be stacked in multiplelayers. To reduce an area necessary for wiring, the size of a substrateis reduced.

If looking in another way, as a circuit formed on the multi-layerprinted wiring board, two kinds of circuits, a circuit (PGK circuit)introduced outside by connecting to the IC chip mounted on the substrateand a circuit (interposer circuit) introduced outside through themulti-layer printed wiring board connected to the IC module are mixed.To connect these effectively, it is preferable to form an externalterminal on each of both faces. This can take roles of the interposerand PKG substrate with a single piece, thereby achieving reduction insize and intensification of function. Even if a fault occurs in themulti-layer printed wiring board or another board, this can beinspected. This can be done before other substrate (IC module) isattached to the multi-layer printed wiring board. Even if anothersubstrate (IC module) is redesigned (for example, in case of memory, ifmeans that its capacity is changed), it can meet easily.

The technical feature of the present invention exists in a multi-layerprinted wiring board loaded with an electronic component such as an ICchip and having external terminals, wherein a bored portion foraccommodating an electronic component is provided in a mounting area andthe external terminals are formed on both faces. The external terminalsmentioned here means a terminal which can be connected outside such asBGA, PGA, bump (solder or metal).

Because the bored portion is formed, the thickness of the mounting area(thickness in a condition in which the IC chip is mounted on themulti-layer printed wiring board) can be reduced. Further, even if theIC chip is constructed into multi-layers, the total thickness of theentire substrate including sealed resin can be reduced.

According to the above-described double face structure, for example,with a printed wiring board loaded with an IC chip connected to thesingle side of the multi-layer printed wiring board, other substrateloaded with an electronic component than the IC chip can be connected tothe opposite face. In other words, this can take a role just like aninterposer. If printed wiring boards including the IC chip are connectedto both faces, this can turn to a stacked structure (three-dimensionalstructure). Particularly, the external terminal can be formed in an areabelow the IC chip.

As shown in FIG. 13, preferably, an external terminal 56 located justbelow on the opposite face does not overlap the external terminal 56.Here, (A1), (B1), (C1) indicate an external terminal in FIG. 2 and (A2),(B2), (C2) are perspective views of the external terminals in (A1),(B1), (C1). This means that an area which the external terminal on theopposite side makes contact with does not overlap an area which theexternal terminal keeps contact with, located just below. As aconsequence, stress generated on the external terminal is prevented frombeing transmitted directly, thereby preventing positional deflection andcontact failure of the terminal and reduction in electric contact andreliability. Because the external terminal is mainly BGA (ball gridarray), bump or the like, its connecting portion is smaller as comparedwith the external terminal such as conductive bump and stress is likelyto be concentrated. Further, although stress is generated due to anexternal factor such as generation of heat (for example, heat cyclecondition) which originates from a difference in thermal expansioncoefficient of materials from other printed wiring board and that stressis transmitted to the external terminal on the opposite side, the stressis relaxed by the substrate or external terminal. Thus, the externalterminal on the opposite face is not affected. If the stress istransmitted directly, defects such as peeling, crack and contact failurewith an outside substrate occur at the connecting portion of theexternal terminals on the opposite face.

Further, preferably, the external terminal on the opposite face does notoverlap the external terminal on the one face or pad area of thatexternal terminal (including land depending on case) located just below.When conductive material such as plating, conductive paste is appliedunder the bottom of the pad of the external terminal, the pad area canbe affected by that stress. By disposing a connecting area of theexternal terminal on the opposite face off that area, it is possible toprotect from an influence of the stress securely.

Preferably, in the mounting area of the electronic component, a via holeis formed and metal layer having a heat radiation function is formed ata portion in the vicinity. Particularly, it is preferable to providemetal layer just below the IC chip and connect that metal layer to theexternal terminal through the via hole (non-through hole). With thisstructure, heat can be transmitted to the printed wiring board sideconnected to the external terminal efficiently to radiate heat.

The external terminal is connected to the via hole in stacked conditionand the via hole connected to the external terminal is preferred to bedeflected from the via hole in an adjacent layer in terms of theircenter line (X1, X2) as shown in FIG. 13.

If the external terminals are formed just on a stacked structure, stressgenerated on one external terminal is transmitted directly into thesubstrate. Thus, the inside of the substrate and the external terminalon the opposite face are affected. If inside the substrate, connectionof the stacked via holes is blocked and in case of the external terminalon the opposite face, contact failure is induced. However, if the viaholes are formed in the stacked condition with their center linesdeflected from each other, transmission of the stress is damped. Aneffect is generated if the inside of the via hole is filled with platingor conductive paste. Filling with the conductive material makes it easyto transmit stress.

Optimally, the multi-layer printed wiring board of the present inventionis constructed by overlaying two or more of the single side circuitboard or double side circuit board in which the non-through holes formedin insulating material are filled with conductive material. As itsmanufacturing method, subtractive method or additive method (includingbuild-up method) is applicable. However, according to the subtractivemethod, if an external terminal is disposed on the structure having athrough hole going through two or more layers, stress cannot be damped.Thus, this method cannot be applied depending on case.

As for the build-up method, if the resin insulating layer containing nocore material is used, forming the bored potion makes it difficult tostabilize the configuration of the resin insulating material. Thus, thismethod cannot be applied depending on the case.

It is preferable to use the single side circuit. The melting point ofthe conductive bump for connecting the single side or double sidecircuit boards is desired to be higher than the melting point ofadhesive agent (for example, solder for bonding the BGA) for theexternal terminal. As a result, melting of the conductive bump itselfcan be blocked. Conversely, if the melting pint of the conductive bumpis lower than the melting point of the adhesive agent of the externalterminal, when the external terminal is mounted, quite a large part ofthe conductive bump is melted by that temperature so that it flows outwithin the substrate. If its flow area is large, the conductive bumpcauses a short-circuit with an adjacent conductive layer. On the otherhand, if the flow area is small, stress is generated between substrates.Unless the stress is relaxed, positional deflection is induced. Thus,the thickness of the conductive bump decreases so that adhesion strengthand electric characteristic drop.

Particularly, the melting point is desired to be 200° C. or more to 350°C. or less. Because the melting point is less than 200° C., a differenceof the melting point relative to solder on the surface layer is small ordecreased, when the IC chip is mounted, melting or diffusion is inducedso that a short-circuit can be generated with an adjacent independentconductor circuit. If the melting point is over 350° C., the metalitself becomes too hard, thereby its connectivity dropping. Thus,connection with the conductor circuit can be disabled. Further, becauseresin as the insulation material is melted if it is intended to melt atthat temperature, the insulation characteristics of the insulationmaterial lowers.

Further, the temperature is more preferred to be in a range of 220° C.to 320° C. In that range, the conductive bump is not diffused even inreliability test under high temperature/high humidity or heat cyclecondition. As the conductive bump, it is permissible to use solder ofSn/Pb, Sn/Ag, Su/Cu, Sn/Zn, Sn/Sb, Sn/Ag/Cu and metal such as tin, zinc.At this time, the melting point is preferred to be 200° C. or more to350° C. or less.

By mixture of Cu, Zn or Sb in the above-described conductive bump, flowof the metal itself can be blocked. That is, Cu alloy, Zn alloy or Znalloy is formed in re-solidified metal. This prevents the alloy frombeing melted by heat generated when it is mounted thereby suppressingdefects such as diffusion of conductive metal. Thus, the possibility ofshort-circuit is diminished to improve the electric characteristic.

Even if at the time of reliability test by heat cycle test or by leavingunder high temperatures, it is left at the time of temperature rise (lowtemperature to high temperature) or high temperatures, re-melting ofsolidified conductive metal is suppressed. Thus, the reliability testcan be improved.

Further, after the reliability test, adhesion strength between theconductive layer and via hole does not drop. Thus, electriccharacteristics does not drop neither and consequently, the electriccharacteristic can be improved. In conductive metal containing Cu, Zn orSb, the fluidity of metal itself is suppressed. For the reason, the viahole pitch can be narrowed more so that it is possible to obtain amulti-layer printed wiring board formed in high density.

As a result of research by the inventor, to solve the above-describedproblem, the technical feature of the present invention exists in amulti-layer printed wiring board in which a mounted electronic componentis wire-bonded from a bonding pad, a substrate being so constructed thata conductive circuit is formed on a single side or double sides ofinsulation material thereof and the non-through hole leading to theconductor circuit is filled with conductive material.

Further, the technical feature of the present invention exists in amulti-layer printed wiring board in which a mounted electronic componentis wire-bonded from a bonding pad, a substrate being so constructed thata conductive circuit is formed on a single side or double sides ofinsulation material thereof and the non-through hole leading to theconductor circuit is filled with conductive material, the substratesbeing overlaid through conductive bump formed on conductive materialfilled in the non-through hole, the conductor circuit just above thenon-through hole filled in the non-through hole being used as thebonding pad.

According to the present invention, by using the conductor circuit justabove the conductor material filled in the non-through hole as a bondingpad, wire can be pulled out to the lower layer through the non-throughholes without pulling out the conductor circuit outward of the substratefrom the conductor circuit and due to the non-through hole, no throughhole area needs to be secured over an entire layer like in the case of athrough hole and the wire can be arranged freely. Thus, although thewiring in the bonding pad area can be performed in high density, deadspace due to unreasonable wiring is eliminated from the surroundingthereby freedom of wiring being increased.

Further, the technical feature of the present invention exists in amulti-layer printed wiring board in which a mounted electronic componentis wire-bonded from a bonding pad, a substrate being so constructed thata conductive circuit is formed on a single side or double sides ofinsulation material thereof and the non-through hole leading to theconductor circuit is filled with conductive material, the non-throughhole being disposed just below the bonding pad by using the conductorcircuit just above the non-through hole as the bonding pad.

Further, the technical feature of the present invention exists in amulti-layer printed wiring board in which a mounted electronic componentis wire-bonded from a bonding pad, a substrate being so constructed thata conductive circuit is formed on a single side or double sides ofinsulation material thereof and the non-through hole leading to theconductor circuit is filled with conductive material, and the substratesbeing overlaid through conductive bump formed on conductive materialfilled in the non-through hole, the non-through hole being disposed justbelow the bonding pad by using the conductor circuit just above thenon-through hole as the bonding pad.

In the present invention, the conductor circuit connected directly toconductive material filled in the non-through hole is used as bondingpad. That is, because the conductor circuit (bonding pad) is connectedto the via hole by filling the non-through hole leading to the conductorcircuit (bonding pad) with conductive material, the conductive material(via hole) and the conductor circuit (bonding pad) can be connectedwithout any via hole land. Because the via hole land having a diameterlarger than the line width of the bonding pad is not employed, thewiring density can be intensified.

Wire can be pulled out to the lower layer through the non-through holeswithout pulling out the conductor circuit outward of the substrate fromthe conductor circuit and due to the non-through hole, no through holearea needs to be secured over an entire layer like in the case of athrough hole and the wire can be arranged freely. Thus, although thewiring in the bonding pad area can be performed in high density, deadspace due to unreasonable wiring is eliminated from the surroundingthereby freedom of wiring being increased.

As the conductive material, plating and conductive paste can be used. Itis preferable to use plating. The reason is that the conductive pastecan cause a sinking after wire is placed.

(Cu Containing Metal Bump)

Because Cu is mixed in the conductive bump, diffusion of metal itselfcan be suppressed. That is, in the metal of solidified conductive bump,Cu alloy is formed. The alloy prevents melting of metal even if it isaffected by various kinds of thermal history (for example, annealing,plating, IC chip mounting process and the like) applied to the substratethereby suppressing defects such as diffusion of conductive bump metal.Thus, changes in resistance, short-circuit and deterioration of electricperformance are suppressed to improve electric characteristics.

Even if at the time of reliability test by leaving under hightemperatures or by heat cycle test, it is left under high temperaturesor under a temperature rise (low temperature to high temperature),re-melting or diffusion of solidified conductive bump is suppressed.

Further, because invasion of water into an interface between theconductive bump and conductive portion is suppressed, generation ofexpansion and contraction due to existence of water content on theinterface is eliminated. Because no partial electric insulation (meaningthat the water content forms a gap) in the vicinity of the interface isgenerated, electric connectivity is secured. Thus, reliability test canbe improved.

Further because no water invades into between the conductive layer andvia hole after the reliability test is carried out, adhesion strength isnot dropped. If water invades, expansion can occurs due to that waterwhen the temperature rises. As a consequence, gap is formed or crack isgenerated so that adhesion property drops. Because they are notgenerated, drop in strength due to decrease in contact condition iseliminated to improve the reliability.

Conductive metal containing Cu is capable of suppressing diffusion ofmetal. Thus, the via hole pitch can be narrowed more and consequently, ahigh density multi-layer printed wiring board can be obtained.

Alloy layer of Cu-conductive metal is formed on the interface betweenthe solidified conductive metal and conductor circuit. The formed alloyfilm serves as protective film to prevent the metal of the other portionof the conductive metal from flowing. Due to the formation of that film,formation of new Cu alloy, particularly, formation in the conductorcircuit is blocked even if influence of heat such as thermal history andthermal process is received, thereby preventing the conductive metalfrom flowing.

For the aforementioned conductive bump, it is preferable to use any oneof Sn—Pb—Cu, Sn/Cu, Sn/Ag/Cu, Sn/Ag/In/Cu, Sn/Cu/Zn. Because Cu is mixedin these, the above-described operation and effect can be obtained byusing the conductive bump.

Because metallic material using lead is limited in its usage as it canbecome a factor for deteriorating the environment, it is preferable touse metallic material not using lead. However, any composition otherthan this can be used as long as Cu is mixed. The mixture ratio of Cu inthe conductive bump is preferred to be 0.1 to 7 wt %.

Because if it is less than 0.1 wt %, the amount of Cu alloy formed afterits solidification is small, when it is re-melted, flow of theconductive bump cannot be suppressed. Thus, connection with anotherconductive layer adjacent is likely to occur. Further, a portion inwhich no Cu alloy film is formed is generated partially on the interfacebetween the conductive metal and conductor circuit. Melting anddiffusion of the conductive metal is generated from that portion inwhich no Cu alloy film is formed. If it exceeds 7 wt %, the meltingpoint rises, so that if it is heated, it is difficult to melt. Thus, theconductive bump itself becomes hard. Because the conductor layer hardenswhen the conductor layer is brought into contact with the via hole,contact failure occurs in the conductor or crack occurs in theconductor, so that its electric connectivity and adhesion property drop.

In the above-mentioned range, the fluidity of the conductive bump can besuppressed and Cu alloy can be formed appropriately to secure adhesionproperty with the conductor.

The reason why the mixture ratio of Cu in the conductive bump ispreferred to be 0.5-5 wt % is that the adhesion strength can beincreased. Because its hardness is appropriate and it can spreaduniformly between the conductors, the electric connectivity is improved.Further, the adhesion property can be improved regardless of the kind ofthe conductive metal (plating, conductive paste, and compound thereof)filling the via hole having the conductive bump.

(Zn Containing Metal Bump)

Because Zn is mixed in the conductive bump, diffusion of the metalitself can be suppressed. That is, Zn alloy is formed in the metal ofsolidified conductive bump. That alloy prevents the metal from beingmelted even if an influence of various thermal histories (for example,annealing, plating, IC chip mounting process and the like) applied tothe substrate is received so as to suppress defects such as diffusion ofconductive bump metal. Thus, changes in resistance, short-circuit anddeterioration of electric performance are suppressed to improve theelectric characteristics.

Further, even if at the time of reliability test by leaving under hightemperatures or by heat cycle test, it is left under high temperaturesor under a temperature rise (low temperature to high temperature),re-melting and diffusion of the solidified conductive bump aresuppressed.

Zn on an interface between the conductive bump and conductor portion orZn alloy layer blocks invasion of metal in the conductor circuit. Thatis, the Zn layer acts as a barrier layer. If heterogeneous substance isformed on the interface, substance having different melting point andthermal expansion is formed as compared with other portions. As aconsequence, expansion and contraction occur because of theheterogeneous substance, so that partial stress is generated in thevicinity of the interface and thus, no insulation property is secured.Thus, the reliability drops.

Because no water invades into between the conductive layer and via holeafter the reliability test is performed, the adhesion strength is notdropped. If water invades, expansion can occur due to that water whenthe temperature rises. As a result, a gap is formed and crack isgenerated so that adhesion property drops. Because such phenomenon doesnot occur, drop in strength due to drop in degree of contact iseliminated, thereby the reliability being raised.

The Zn containing conductive metal is capable of suppressing diffusionof the metal. The reason is that the melting point is likely to rise.Thus, the via hole pitch can be narrowed more, so that a high densitymulti-layer printed wiring board can be obtained.

Alloy layer of Zn-conductive metal is formed on an interface between thesolidified conductive metal and conductor circuit. The formed alloy filmturns to protective film to prevent the metal of the other portion ofthe conductive metal from flowing. Because even if an influence of heatsuch as thermal history and thermal process is received, due to theformation of that film, formation of new Zn alloy, particularlyformation of the conductor circuit is prevented, thereby suppressingflow of the conductive metal.

It is preferable that any one of Sn/Zn, Sn/Ag/Zn, Sn/Cu/Zn is used forthe aforementioned conductive bump. Because Zn is mixed in thesecomponents, the above-described operation and effect are obtained byusing the conductive bump.

Further, because the metallic material using lead is limited in usage asit can turn to a factor which deteriorates the environment, it ispreferable to use metallic material using no lead. However, compositionof the solder other than this can be used as long as Zn is mixedtherein.

The mixture ratio of Zn in the conductive bump is preferred to be 0.1-10wt %.

Because if it is less than 0.1 wt %, the amount of Zn alloy formed afterits solidification is small, when it is re-melted, flow of theconductive bump cannot be suppressed. Thus, connection with anotherconductive layer adjacent is likely to occur. Further, a portion inwhich no Zn alloy film is formed is generated partially on the interfacebetween the conductive metal and conductor circuit. Melting anddiffusion of the conductive metal is generated from that portion inwhich no Zn alloy film is formed.

If it exceeds 10 wt %, the melting point rises, so that if it is heated,it is difficult to melt. Thus, the conductive bump itself becomes hard.Because the conductor layer hardens when the conductor layer is broughtinto contact with the via hole, contact failure occurs in the conductoror crack occurs in the conductor, so that its electric connectivity andadhesion property drop.

In the above-mentioned range, the fluidity of the conductive bump can besuppressed to secure adhesion property with the conductor. The reasonwhy the mixture ratio of Zn in the conductive bump is preferred to be0.5-9 wt % is that the adhesion strength can be increased. Because itshardness is appropriate and it can spread uniformly between theconductors, the electric connectivity is improved. Further, the adhesionproperty can be improved regardless of the kind of the conductive metal(plating, conductive paste, and compound thereof) filling the via holehaving the conductive bump.

It is permissible to use metal containing antimony. In this case,antimony takes the same role as lead. That is, antimony takes a role asbarrier layer to prevent formation of alloy layer with copper. Themixture ratio of antimony is preferred to be 0.1-10%. Because if it isless than 0.1 wt %, the amount of antimony alloy formed after itssolidification is small, when it is re-melted, fluidity of theconductive bump cannot be suppressed. Thus, connection with anotherconductive layer adjacent is likely to occur. Further, a portion inwhich no antimony alloy film is formed is generated partially on theinterface between the conductive metal and conductor circuit. Meltingand diffusion of the conductive metal is generated from that portion inwhich no antimony alloy film is formed.

If it exceeds 10 wt %, the melting point rises, so that if it is heated,it is difficult to melt. Thus, the conductive bump itself becomes hard.Because the conductor layer hardens when the conductor layer is broughtinto contact with the via hole, contact failure occurs in the conductoror crack occurs in the conductor, so that its electric connectivity andadhesion property drop. In the above-mentioned range, the adhesion withthe conductor can be secured while suppressing fluidity in theconductive bump.

In addition to these, it is permissible to use generally used solderpaste or conductive paste such as Sn/Pb, Sn/Ag, Sn/Ag/Cu.

(Description of Single Side Circuit Board)

For the single side circuit board as a basic unit which constitutes themulti-layer printed wiring board of the present invention, it isdesirable to use hard single side copper foil attached resin basematerial formed of completely hardened resin material as insulating basematerial. Because due to application of such a substrate, a deflectionof final dimension of the insulating base material due to pressing isdiminished (no contraction) when other single side board is pressed byheat pressing to form the multi-layer structure, the positionaldeflection of the via hole can be suppressed to its minimum extentthereby reducing the diameter of the via land. Therefore, the wiringpitch can be reduced to improve the wiring density. Further, because thethickness of the substrate can be maintained constant, if an opening forforming a filling via hole described later is formed by laserprocessing, laser irradiation condition can be set easily.

As the insulating resin base material, it is preferable to use hardsubstrate selected from glass fabric epoxy resin base material, glassfabric bsmaleimide-triazine resin base material, glass fabricpolyphenylene ether resin base material, aramid unwoven fabric-epoxyresin base material, aramid unwoven fabric—polyimide resin base materialand glass fabric epoxy resin base material is most preferable.Additionally, it is permissible to use thermo setting resin such aspolyimide, compound material, photo sensitive resin and photo curingresin as the thermoplastic resin. Inorganic filler such as glass,alumina, zirconia may be dispersed in the resin of the insulating resinbase material.

The thickness of the insulating base material is preferred to be 20-600μm. The reason is that if the thickness is less than 20 μm, the strengthdrops so that it becomes difficult to handle and reliability on theelectric insulation property lowers. Another reason is that shapeholding characteristic when a bored portion is formed can drop. Stillanother reason is that if it exceeds 600 μm, a fine opening forformation of the via hole becomes difficult to form and the substrateitself becomes thick.

The conductive layer or the conductor circuit formed on a single side ofthe insulating base material is formed by bonding copper foil to theinsulating base material via appropriate resin adhesive agent andetching that copper foil.

Preferably, the aforementioned conductive layer is formed by pressingthe copper foil of 5-50 μm thickness with heat onto the insulating basematerial via resin adhesive agent layer held in semi-hardening conditionand as for the conductor circuit, after the copper foil is pressed withheat, a photo sensitive dry film is bonded to the copper foil face orliquid photo sensitive resist is applied and with a mask having apredetermined wiring pattern placed, plating resist layer is formed byexposure to light and development and after that, the copper foil at aportion in which no etching resist is formed is etched to form thatconductor circuit.

After the conductor circuit is formed, an opening is made with router orby laser or punching. The size of the opening is, if considering thesubstrate as a single piece, preferred to be 10-70% the area of thatsubstrate. Because if it is less than 10%, the formation area of thebored portion is small, a merit of the formation is little. Because ifit exceeds 70%, a strength withstanding pressing cannot be maintainedand the area for forming the external terminal decreases, the IC chip tobe mounted may be limited.

The pressing of the copper foil onto the insulating base material withheat is carried out at an appropriate temperature and under anappropriate pressure and more preferably, it is carried out under areduced atmospheric pressure, and because the copper foil is bondedfirmly to the insulating base material by hardening only the resinadhesive agent layer in the semi-hardening condition, manufacturing timeis reduced as compared with a conventional circuit substrate usingprepreg.

If any bored portion is formed at this time, it is preferable to useprotective film to protect the bored portion and prevent flow ofadhesive agent on the interface.

Instead of bonding of the copper foil onto the insulating base material,it is permissible to adopt a single side copper stretched laminatedboard in which the copper foil is bonded on the insulating base materialand etch this single side copper stretched laminated board with at leastone selected from sulfuric acid-hydrogen peroxide, persulfate, cupricchloride and ferric chloride solutions.

Preferably, a land (pad) is formed on the surface corresponding to eachvia hole in the conductor circuit as part of the conductor circuit suchthat the diameter thereof is in a range of 50-250 μm.

If the via holes are provided in a stacked condition, it is desirable todeflect the center lines of the via holes from each other. As a result,the stress which is transmitted through the stacked structure can bedamped.

Preferably, roughing layer is formed on the surface of a wiring patternof the conductor circuit to improve adhesion with adhesive agent layerfor bonding together the circuit substrates, thereby preventinggeneration of separation (delamination).

As the roughing treatment method, for example, soft etching treatment,blacking (oxidation)—reduction treatment, formation of needle-like alloyplating of copper-nickel-phosphorus (made by EBARA YUJIRAITO; productname, INTERPLATE) and surface roughing with etching solution named “MECETCH BOND” made by MEC are available.

Preferably, the opening for formation of the via hole formed such thatit reaches the conductor circuit from the surface on an opposite side tothe surface of the insulating resin base material having such aconductor circuit is formed with carbon dioxide laser projected under acondition of pulse energy of 0.5-100 mJ, pulse width of 1-100 μs, pulsewidth of more than 0.5 ms and number of shots of 3-50 and the diameterof its opening is preferred to be in a range of 50-250 μm.

The reason is that if it is less than 50 μm, it is difficult to fill theopening with conductive substance and connecting reliability drops andif it exceeds 250 μm, forming in high density is difficult.

Before forming the opening with carbon dioxide laser, preferably, resinfilm is bonded to the surface on an opposite side to the conductorcircuit forming face of the insulating base material and the resin filmis irradiated with laser.

This resin film functions as protective mask upon filling the inside ofan opening with metallic plating by electrolytic plating treatment afterde-smear treatment of the inside of the opening for formation of the viahole and further as a printing mask for forming a projecting conductor(conductive bump) just above the metallic plating layer of the via hole.

As for the resin film, its adhesive agent layer is 1-20 μm thick andpreferably, it is formed with PET film whose thickness is 10-50 μm.

The reason is that because the height of the projecting conductordescribed later is determined depending on the thickness of the PETfilm, if the thickness is less than 10 μm, the projecting conductor isso low that contact failure is likely to occur and if the thickness isover 50 μm, the projecting conductor spreads so much on a connectinginterface, that a fine pattern cannot be formed.

To form the via hole by filling the inside of the opening for formationof the via hole with conductive material, it is desirable to fill withplating or conductive paste.

Although filling with conductive paste is suitable to simplify thefilling process to reduce manufacturing cost and improve yield,contraction by hardening can become too large depending on thecomposition ratio in the paste (conductive metal, resin, hardening agentand the like). Plating is more desirable from viewpoint of the shapeafter the filling and connecting reliability.

Although the aforementioned filling with plating can be carried out byelectrolytic plating treatment or electroless plating treatment,metallic plating formed by electrolytic plating treatment, for example,metallic plating with tin, silver, solder, copper/tin, copper/silver orthe like is preferable, particularly, electrolytic copper plating isoptimal.

When filling by the electrolytic plating treatment, with protective filmbonded to the copper foil bonding face (conductor circuit forming face)of the insulating base material, the electrolytic plating is performedwith the copper foil formed on the insulating base material as platinglead. Because this copper foil (metallic layer) is formed over an entiresurface of one of the insulating base material, current density isequalized and consequently, the opening for formation of the via holecan be filled with electrolytic plating in a uniform height.

Before the electrolytic plating, it is recommendable to activate thesurface of the metallic layer within the non-through hole with acid.

Further, preferably, after the electrolytic plating is carried out, theelectrolytic plating (metal) swollen from an opening edge is removed bybelt sander polishing, buffing or the like so that it is flattened.

Instead of filling with conductive substance by plating treatment, it ispermissible to apply a method of filling with conductive paste or fillpart of the opening by electrolytic plating treatment or electrolessplating treatment while filling a remaining portion with conductivepaste.

As the conductive paste, it is permissible to use conductive pastecomposed of metallic particles of at least one kind selected fromcopper, tin, gold, silver, nickel and various kinds of solders.

As the metallic particle, it is permissible to use the one whose surfaceis coated with heterogeneous metal. More specifically, a metallicparticle obtained by coating the surface of copper particle withprecious metal selected from gold and silver can be used.

As the conductive paste, organic conductive paste obtained by addingthermal setting resin like epoxy resin or polyphenylene sulfide (PPS)resin to metallic particle is desirable.

Because the opening formed by the laser processing has a fine diameterof 20-150 μm, bubbles are likely to be left when filling with conductivepaste. Thus, filling by electrolytic plating is practical.

As for the via hole to be formed in the single side circuit board, itsarrangement density is the largest in case of a single side circuitboard to be overlaid outside for loading with LSI chip or the like andit is the smallest in case of other single side circuit board outside tobe connected to a mother board. That is, preferably, a distance betweenthe via holes formed in respective circuit boards to be overlaidincreases as it goes from a circuit board on the side loaded with theLSI chip or the like to a circuit board on the side to be connected tothe mother board. With such a structure, the ability of placing wirearound is improved.

Upon manufacturing the multi-layer printed wiring board of the presentinvention, preferably, the single side circuit board as a basic unit tobe overlaid is provided with the projecting conductor or conductive bumpon the via hole so as to secure electric connection with other singleside circuit board.

Preferably, this conductive bump is formed by filling the inside of theopening in the protective film formed by irradiation of laser withplating or conductive paste.

Although the filling with plating can be carried out by electrolyticplating treatment or electroless plating treatment, the electrolyticplating treatment is preferable.

Although the electrolytic plating can use copper, gold, nickel, tin andvarious kinds of solders, which have a low melting point, plating withtin or plating with solder is optimal.

The height of the conductive bump is preferred to be in a range of 3-60μm. The reason is that if it is less than 3 μm, a deflection of theheight of the bump is not allowable due to deformation of the bump andif it exceeds 60 μm, the resistance value increases and when the bump isformed, it spreads laterally thereby causing a short-circuit.

If the conductive bump is formed by filling with conductive paste,deflection of the height of electrolytic plating forming the via hole iscorrected by adjusting the amount of conductive paste to be filled sothat the heights of many conductive bumps can be arranged uniformly.

The bump composed of conductive paste is preferred to be insemi-hardening condition. The reason is that the conductive paste ishard even in the semi-hardening condition and it can penetrate intoorganic adhesive agent layer softened at the time of heat pressing.Another reason is that not only it deforms at the time of heat pressingso that its contact area increases thereby reducing conductionresistance but also the deflection of the height of the bumps can becorrected.

Additionally, the conductive bump can be formed according to, forexample, a method of screen-printing the conductive paste using a metalmask having an opening at a specified position, a method of printingsolder paste of low melting point metal, a method of dipping into meltedsolder solution or by electroless or electrolytic plating.

The low melting point metals preferable to use include Sn—Ag base, Sn—Sbbase solder, Sn—Pb base solder, Sn—Zn base solder, Sn—Pb—Cu base solder,Sn—Cu base solder, Ag—Sn—Cu base solder, In—Cu base solder, Sn—Cu—Znbase solder which contain Cu. More specifically, Sn/Pb/Cu, Sn/Cu,Sn/Ag/Cu, Sn/Ag/In/Cu, Sn/Cu/Zn, Sn/Zn, Sn/Sb, Sn/Sb/In and metals suchas tin and lead can be mentioned. Basically, it is preferable to usesolder containing Cu, Zn or Sb. The reason is that they are capable ofsuppressing fluidity of conductive paste and under reliability testunder high temperature/high humidity or under heat cycle, more excellentthan other materials in terms of electric connectivity and reliability.

In the multi-layer printed wiring board of the present invention, asdescribed above, plural pieces of the single side circuit boards inwhich a conductor circuit is formed on a single side of insulating basematerial thereof are overlaid in a predetermined direction and copperfoil whose one face is subjected to mat treatment is pressed against thesurface on the conductive bump side of the single side circuit boarddisposed inside of those single side circuit boards such that the matface opposes so as to form a conductor circuit having a predeterminedwiring pattern by etching treatment.

The mat face of the copper foil is preferred to be formed by well knownetching, electroless plating, oxidation-reduction treatment or the like,particularly, it is preferred to be formed by etching.

For the etching treatment, cupric chloride, ferric chloride,persulfates, hydrogen peroxide/sulfuric acid, alkali etchant, andetching solution using organic acid and cupric complex are available.

For the electroless plating treatment, electroless plating for a singlelayer of copper, nickel, aluminum, displacement plating, compositecoatings of copper—nickel—phosphorus are available.

As the oxidation reduction treatment, a treatment by reduction bathingas blacking bathing and alkali bathing with sodium is available.

Although adhesion property between the mat treated copper foil andinsulating resin base material differs depending on resin viscosity,thickness of the copper foil, heat press pressure and the like, if theinsulating resin base material is hard resin base material and thethickness of the copper foil is in a range of 5-50 μm, preferably, theroughness of the mat face of the copper foil is in a range of 0.1-5 μm,the temperature is 120-250° C., the heat pressing pressure is in a rangeof 1-10 Mpa, and consequently, the peeling strength is in a range of 0.6to 1.4 Kg/cm².

Because the mat face of the copper foil is pressed against not only theface on the conductive bump side of the single side circuit board butalso the conductive bump projecting form that face, adhesion propertybetween the conductor circuit formed by etching the copper foil and theface on the conductive bump side and between the conductor circuit andthe conductive bump is improved.

Generally, because if the single side circuit boards are overlaid into amulti-layer structure in the same direction, heating process such asdrying and annealing is repeated after dipped in plating solution orcleaning liquid, stress applied to a portion in which no conductorcircuit exists of the metallic layer is not damped. Thus, the substrateis warped, so that breaking of the conductor circuit, breaking ofwiring, contact failure at the via hole or peeling of filled metaloccurs thereby causing drops in electric connectivity and reliability.

However according to the present invention, after the plural single sidecircuit boards overlaid in the same direction and the copper foil areintegrated by heat press, a conductor circuit is formed by etching thecopper foil and other single side circuit board is placed on thatconductor circuit forming face in an opposite direction to theaforementioned direction and integrated by heat press.

In this case, the mat face of the copper foil is pressed against theface on the conductive bump side of the single side circuit boardlocated inside and the conductor circuit is formed by etching the copperfoil. This conductor circuit can be formed into a desired wiring patternhaving at least conductive pad to be joined with the conductive bump onthe other single side circuit board to be overlaid.

Therefore, peeling strength and pull strength of the conductor circuitto the face on the conductive bump side of the substrate are securedsufficiently and deflection in position of the conductor pad to the viahole by heat press can be prevented thereby securing electricconnection.

In this case, the heat press is preferred to be carried out twice.Although an accurate scale factor is needed, a high peeling strength andpull strength can be obtained.

It is permissible to form protective film of at least one kind selectedfrom tin, zinc, nickel, and phosphorous or protective film of preciousmetal such as gold or platinum to the mat face of the copper foil whichforms the conductor circuit.

The thickness of the protective film is preferred to be in a range of0.01-3 μm. The reason is that if it is less than 0.01 μm, fineunevenness of the mat face cannot be covered completely and if itexceeds 3 μm, the protective film is loaded in the concave portions inthe formed mat face, thereby mat treatment effect being killed.Particularly preferably, the thickness of the film is in a range of0.03-1 μm.

Of the protective films, protective film made of tin is formed as thinfilm deposited by electroless displacement plating and because itsadhesion property with the mat face is excellent, it can be applied mosteffectively.

For the electroless plating bathing for forming such tin containedplating film, tin boronfluoride—thiourea solution or tinchloride—thiourea solution is used and preferable plating condition isabout five minutes at room temperature around 20° C., and about 1minutes at high temperatures of 50° C. to 60° C.

According to such electroless plating treatment, copper-tin displacementreaction based on formation of metal complex of thiourea occurs on thesurface of copper pattern so that thin tin film is formed. Due tocopper-tin displacement reaction, the mat face can be covered withoutdamaging the uneven configuration.

Precious metal which can be used instead of tin or the like is preferredto be gold or platinum. The reason is that such precious metal is harderto be attacked by acid or oxidant as roughing treatment solution thancopper and it can cover the mat face easily. However, because theprecious metal boosts its cost, it is often used for only high valueadded products. Film of gold or platinum can be formed by spattering,electrolytic plating or electroless plating.

Provision of such covering layer equalizes the wettability of the matface so that not only connectivity with the conductive bump formedcorresponding to the via hole can be improved but also connectivity withresin impregnated in core material constituting the resin insulatinglayer can be improved. As a result, the electric connectivity andconnection reliability are improved largely.

The multi-layer printed wiring board formed by overlaying and heat presscan be provided with solder resist layer covering the surface of acircuit board outside.

The solder resist layer is formed of mainly thermal setting resin orphoto sensitive resin and an opening is formed at a portioncorresponding to the via hole position on the circuit board and solderedbodies such as a soldered bump, soldering ball, T-shaped conductive pinare formed as an external terminal on the conductive circuit (conductivepad) exposed from that opening. The external terminals are formed onboth faces.

Of the circuit boards located outside, other circuit board on a lowerlayer on a side connected to a mother board can be provided with aT-shaped conductive pin formed of metallic material such as 42 alloy,phosphor bronze or a conductive ball formed of metallic material such asgold, silver, solder, located just above the via hole.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(A) is a sectional view of a multi-layer printed wiring boardaccording to a first embodiment of the present invention and FIG. 1(B)is a sectional view showing a condition in which an IC chip is mountedon the multi-layer printed wiring board;

FIG. 2 is a sectional view showing a condition in which the IC module ismounted on the multi-layer printed wiring board shown in FIG. 1(B);

FIG. 3 is a manufacturing process diagram of a single side circuit boardconstituting the multi-layer printed wiring board shown in FIG. 1;

FIG. 4 is a manufacturing process diagram of a single side circuit boardconstituting the multi-layer printed wiring board shown in FIG. 1;

FIG. 5 is a manufacturing process diagram of a single side circuit boardconstituting the multi-layer printed wiring board shown in FIG. 1;

FIG. 6 is a manufacturing process diagram of a single side circuit boardconstituting the multi-layer printed wiring board shown in FIG. 1;

FIG. 7 is a manufacturing process diagram of the multi-layer printedwiring board shown in FIG. 1;

FIG. 8 is a manufacturing process diagram of the multi-layer printedwiring board shown in FIG. 1;

FIG. 9 is a manufacturing process diagram of the multi-layer printedwiring board according to a first modification of the first embodiment;

FIG. 10 is a manufacturing process diagram of the multi-layer printedwiring board according to a second modification of the first embodiment;

FIG. 11(A) is a sectional view of the multi-layer printed wiring boardaccording to a modification of the first embodiment and FIG. 11(B) is aplan view;

FIG. 12 is a sectional view of the multi-layer printed wiring boardaccording to a modification of the first embodiment;

FIGS. 13(A1), (B1), (C1) show the external terminal in FIG. 2 inenlargement and FIGS. 13(A2), (B2), (C2) are perspective views of theexternal terminals in (A1), (B1), (C1);

FIG. 14(A) is a sectional view showing a via hole according to a change1 of a example 1, FIG. 14(B) is a sectional view showing a via holeaccording to a change 2 of the example 1 and FIG. 14(C) is a sectionalview showing a via hole according to a change 3 of the example 1;

FIGS. 15(A), (B), (C) are explanatory diagrams of the multi-layerprinted wiring board according to a conventional technology;

FIG. 16 is a diagram comparing results of conduction test between theexample 1 and comparative examples 1, 2;

FIG. 17(A) is a sectional view showing the structure of the multi-layerprinted wiring board according to a second embodiment of the presentinvention, and FIG. 17(B) is a sectional view showing a condition inwhich the IC chip is loaded on the multi-layer printed wiring board;

FIG. 18(A) is a sectional view showing a condition in which the IC chip70 of the multi-layer printed wiring board shown in FIG. 17(A) is moldedwith resin and FIG. 18(B) is a sectional view showing a condition inwhich the IC module is loaded on the multi-layer printed wiring boardshown in FIG. 18(A);

FIG. 19(A) is a plan view of the multi-layer printed wiring board shownin FIG. 9(C) and FIG. 19(B) is a plan view of the multi-layer printedwiring board shown in FIG. 17(B);

FIG. 20(A) is a plan view of the multi-layer printed wiring board shownin FIG. 18(A) and FIG. 20(B) is a plan view of the multi-layer printedwiring board according to a modification of the second embodiment;

FIG. 21(A) is a sectional view of the multi-layer printed wiring boardaccording to a third embodiment and FIG. 21(B) is a sectional viewshowing a condition in which the IC chip is loaded on the multi-layerprinted wiring board;

FIG. 22(A) is a plan view of the multi-layer printed wiring board ofFIG. 21(A) and FIG. 22(B) is a plan view of the multi-layer printedwiring board of FIG. 21(B);

FIG. 23 is a diagram comparing results of conduction test between theexample 2 and the comparative examples 3, 4; and

FIG. 24(A) is a plan view of the multi-layer printed wiring boardaccording to the conventional technology and FIG. 24(B) is a sectionalview of the multi-layer printed wiring board of FIG. 24(A).

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments

First, the structure of the multi-layer printed wiring board in whichthe single side circuit boards are multi-layered according to the firstembodiment of the present invention will be described with reference toFIGS. 1, 2.

FIG. 1 shows the structure of the multi-layer printed wiring board 100constituting a package substrate and FIG. 1(B) shows a condition inwhich an IC chip 70 is mounted on the multi-layer printed wiring board100. FIG. 2 shows a condition in which an IC module 120 is mounted onthe multi-layer printed wiring board 100 loaded with the IC chip 70.

As shown in FIG. 1(A), the multi-layer printed wiring board 100 isproduced by stacking a single side circuit board A of two layers and asingle side circuit board B. An opening (bored portion) 10 a foraccommodating the IC chip is formed in the center of the upper singleside circuit board A. A conductor circuit 36 is formed on the top faceof the single side circuit board A and a BGA 56 for connecting the ICmodule is disposed on the conductor circuit 36. A via hole 18 is formedin an opening 16 going through an insulating base material 10 below theconductor circuit 36. At a bottom end of the via hole 18 is disposed asoldered bump 24 for connecting to the conductor circuit 28 of the lowersingle side circuit board B. The single side circuit board A and thelower single side circuit board B are connected through adhesive agentlayer 26. Metallic layer 28 a for radiating heat of the IC chip 70 isprovided in the center of the top face of the lower single side circuitboard B. A via hole 18 a for heat radiation is provided below themetallic layer 28 a. The via hole 18 for connecting the circuit isprovided below the upper conductor circuit 28 of the lower single sidecircuit board B. A conductor circuit 38 is connected to the solderedbump 24 of the lower single side circuit board B and the BGA 56 ismounted on the conductor circuit 38. In the meantime, the top face ofthe single side circuit board A and the bottom face of the single sidecircuit board B are covered with solder resist layer 40.

As shown in FIG. 1(B), the IC chip 70 is accommodated in the opening 10a of the multi-layer printed wiring board 100 and on the metallic layer28 a. The IC chip 70 is connected to a conductor circuit (pad) 36 p onthe side of the multi-layer printed wiring board through wire 72. The ICchip 70 and opening 10 a are molded by resin 74.

As shown in FIG. 2, an IC module 120 is connected to the BGA 56 on thefront face side of the multi-layer printed wiring board 100 through aterminal 132. On the other hand, the BGA 56 on the back side of themulti-layer printed wiring board is connected to a printed wiring boardor the like (not shown). The IC module 120 molds the IC chip 122 mountedon a terminal plate 130 with resin 124 and the IC chip 122 and theterminal 132 of the terminal plate 130 are bonding-connected throughwire 128.

Because the BGAs 56 are disposed on the front face and rear face of themulti-layer printed wiring board 100 of the first embodiment, anotherprinted wiring borad can be connected to each of the both surfaces. Forexample, with the IC module 120 mounted through the BGA 56 on the frontface, the printed wiring board can be connected through the BGA 56 onthe rear face. Further, freedom in the configuration of the IC module tobe mounted increases.

If looking in another way, as a circuit formed on the multi-layerprinted wiring board, two kinds of circuits, a circuit (PGK circuit)introduced outside by connecting to the IC chip 70 mounted on thesubstrate and a circuit (interposer circuit) introduced outside throughthe multi-layer printed wiring board connected to the IC module 120 aremixed. This can take roles of the interposer and PKG substrate with asingle piece thereby achieving reduction in size and intensification offunction. In this case, if a trouble occurs in the multi-layer printedwiring board 100 or the IC module 120, this can be treated beforemounting the IC module 120 on the multi-layer printed wiring board. Evenif the IC module 120 is redesigned (for example, in case of memory,means a case where its capacity is changed or the like), this board canmeet it easily.

Because the bored portion 10 a is formed, the thickness of the mountingarea (thickness in a condition with the IC chip 70 mounted on themulti-layer printed wiring board 100) can be reduced. Further, even ifthe IC is constructed in multi-layers, the total thickness of thesubstrate including sealing resin can be reduced.

According to the first embodiment, the BGAs 56 on the rear face aredisposed just below the BGAs 56 and the pad 36 p on the front face suchthat they do not overlap. As shown in FIG. 13 indicating part of FIG. 2by enlargement, a center line X1 of a via hole 18 on which the BGA 56 isto be mounted is deflected from a center line X2 of a via hole 18 onwhich the BGA on the rear face is to be mounted. That is, the BGAs 56 onthe rear face are disposed just below a connection area of the BGAs 56and the pad on the front face such that the connection area of the BGAs56 on the rear face does not overlap. The BGA 56 has a smallerconnection portion than an external terminal such as conductiveconnecting pin, so that stress is likely to be concentrated. The reasonis that if the thermal expansion coefficient of material is differentfrom other printed wiring board, stress is generated due to an externalfactor such as application of heat and that stress is transmitted to anouter end. Thus, the generated stress is transmitted to a substrate. Ifthe BGAs 56 on both sides are formed such that they overlap, stress istransmitted to the opposite side. Consequently, connection failure mayoccur on the opposite side. However, if the BGAs 56 do not overlap, thestress is relaxed thereby making connection failure difficult to induce.

According to the first embodiment, the IC chip 122 is a memory having asmall heat release value and the IC chip 70 is a logic IC having a largeheat release value. The metallic layer 28 a is provided just under thisIC chip 70 so that the metallic layer 28 a is connected to the BGA 56through the via hole 18 a. With this configuration, heat is transmittedeffectively to the printed wiring board side connected to the BGAs 56and radiated.

FIG. 11(A) is a sectional view of the multi-layer printed wiring boardaccording to a modification of the first embodiment and FIG. 11(B) is aplan view. According to this modification, the pads 36 p are disposed instaggered fashion.

FIG. 12 is a sectional view of the multi-layer printed wiring boardaccording to a modification of the first embodiment. As thismodification indicates, the IC chips 122B can be stacked on the IC chip122A.

Hereinafter, an example of the manufacturing method of the multi-layerprinted wiring board of the first embodiment will be described in detailwith reference to the accompanying drawings.

-   (1) Upon manufacturing the multi-layer printed wiring board of the    present invention, the single side circuit board 10A which is a    basic unit constituting it is a starting material in which copper    foil 12 is bonded on a single side of the insulating base material    10 (FIG. 3(A)).

Although as this insulating base material, a hard layered base materialselected from for example, glass fabric epoxy resin base material, glassfabric bismaleimide-triazine resin base material, glass fabricpolyphenylene ether resin base material, aramid unwoven fabric—epoxyresin base material, aramid unwoven fabric—polyimide resin base materialmay be used, the glass fabric epoxy resin base material is mostpreferable. Inorganic fillers such as glass, alumina and zirconia may bedispersed in the resin of the insulating base material.

The insulating base material 10 is preferred to be 20-600 μm thick. Thereason is that if the thickness is less than 20 μm, its strength dropsso that it is difficult to handle and reliability on electric insulationlowers and if the thickness exceeds 600 μm, it is difficult to form afine via hole and charge with conductive paste and the board itselfbecomes thick.

The thickness of the copper foil 12 is preferred to be 5-18 μm. Thereason is that when an opening for via hole formation is made in theinsulating base material by laser processing, if the base material istoo thin, it is bored through and conversely if it is too thick, aconductor circuit pattern having a fine wire width is difficult to formby etching.

As for the insulating base material 10 and the copper foil 12, it ispreferable to use a single side copper stretched layered board obtainedby laying prepreg as B stage obtained by impregnating glass cloth withepoxy resin and copper foil and then pressing with heat. The reason isthat during handling after etching of the copper foil, the positions ofthe wiring pattern and via hole do not deflect thereby ensuring anexcellent position accuracy.

-   (2) Next, transparent protective film 14 is bonded to the surface on    an opposite side to the surface on which the copper foil as the    insulating base material is bonded (FIG. 3(B)).

As this protective film 14, polyethylene terephthalate (PET) film whoseadhesive agent layer is 1-20 μm thick while its own thickness is 10-50μm is used.

-   (3) Next, by irradiating the PET film 14 bonded on the insulating    base material with carbon dioxide laser, the opening 16, which goes    through the PET film from the front face of the insulating base    material 10 to the copper foil (or conductor circuit pattern) 12 is    formed (FIG. 3(C)).

This laser processing is carried out with a pulse oscillation typecarbon dioxide laser processing unit and as the processing condition,preferably, pulse energy is 0.5 to 100 mJ, pulse width is 1 to 100% s,pulse interval is 0.5 ms or more and the number of shots is in a rangeof 3 to 50.

The diameter of the via forming opening 16 formed under such a conditionis preferred to be 5 to 250 μm.

If the soldered bump described later is formed by printing withconductive paste, the protective film can be used as a print mask. Inthis case, it is preferable to use solder mixed with Cu, Zn or Sb.Because they have a high melting point as compared with Sn/Pb and thefluidity of its paste is small, short-circuit (short-circuit) withanother adjoining conductor circuit is unlikely to occur. As a result,the electric connectivity and connection reliability are improved.However, it is permissible to use generally used paste such as Sn/Pb,Sn/Ag and conductive paste composed of metallic particles such as copperand gold.

-   (4) To remove resin residue collected on the side face and bottom    face of the opening 16 formed in the step (3), de-smear treatment is    carried out.

Preferably, this de-smear treatment is carried out by dry treatment suchas oxygen plasma discharge treatment, corona discharge treatment,ultraviolet laser treatment or excimer laser.

-   (5) Next, after the PET film 15 is bonded to the surface of the    copper foil 12 of the de-smeared substrate 10 as plate protective    film (FIG. 3(D)), electrolytic copper plating treatment is carried    out with the copper foil 12 as plating lead to fill the opening with    electrolytic copper plating in order to form a filled via hole 18    (FIG. 3(E)).

After electrolytic copper plating treatment, it is permissible torelease the PET film 15 bonded to the substrate and remove theelectrolytic copper plating swollen on the top of the opening by beltsander polishing or buffing to flatten (FIG. 4(A)).

-   (6) After the electrolytic copper plating treatment of the (5),    electrolytic soldering is carried out with the copper plating 18 as    plating lead. By plating, projecting conductor made of electrolytic    solder plating, that is, conductive bump 24 is formed such that it    projects slightly from the surface of the electrolytic copper    plating 18 (FIG. 4(B)). The conductive bump formed at this time is    formed of Sn/Cu (97:3).-   (7) After the adhesive agent layer 26 is formed by coating the    surface of the insulating base material 10 containing the conductive    bump 24 with resin adhesive agent, the PET film bonded on the copper    foil 12 of the insulating base material 10 is released (FIG. 4(C)).

The resin adhesive agent is applied on the entire surface of theinsulating base material containing the conductive bump or the surfacecontaining no conductive bump to form adhesive agent layer composed ofdried uncured resin. This adhesive agent layer is preferred to bepre-cured to facilitate its handling and its thickness is preferred tobe in a range of 5 to 50 μm.

The adhesive agent layer is preferred to be formed of organic adhesiveagent and the organic adhesive agent is preferred to be at least oneresin selected from epoxy resin, polyimide resin, thermosettingpolyphenolene ether (PPE), composite resin of epoxy resin andthermoplastic resin, composite resin of epoxy resin and silicone resinand BT resin.

Coating with the uncured resin which is organic adhesive agent can becarried out using a curtain coater, spin coater, roll coater, spraycoater, screen printing or the like. Further, formation of the adhesiveagent can be carried out by laminating with adhesive agent sheet.

At this time, two kinds of the single side circuit boards are created.One of them is a single side circuit board (hereinafter referred to assingle side circuit board A) having the opening 10 a in the substrate,created with a router or by punching (FIG. 4(D)).

Another is a single side circuit board (hereinafter referred to assingle side circuit board B) having no opening, described later.

The single side circuit board A produced through the steps (1)-(7) hasan opening in the substrate, created with router, punching, laser or thelike. Its formation area is more than 3% the area of the IC chipmounted. The reason is that because if it is less than 2%, an allowanceto unavoidable deflection in position of alignment of the IC chip or thelike is eliminated, the IC chip cannot be mounted. Another reason isthat there is secured no area for mounting.

When forming the multi-layer printed wiring board of the presentinvention in which the copper foil is provided as conductive layer onone surface of the insulating base material, a filled via hole isprovided in an opening which reaches the copper foil from the othersurface, soldered bump is formed of solder plating on that filled viahole and adhesive agent layer is formed on the surface of the insulatingbase material containing the soldered bumps, this is preferred to beemployed as a circuit board located on an upper layer and to be overlaidor a circuit board which forms a double side circuit board together withthe copper foil having a mat face.

Next, another single side circuit board B intended to be laid under thesingle side circuit board A is produced.

-   (8) First, after the same processing as the steps (1)-(6) is carried    out (FIG. 5(A)-(G)), etching protective film 25 is bonded to the    soldered bump 24 forming face of the insulating base material 10    (FIG. 6(A)) and the copper foil 12 is covered with a predetermined    circuit pattern mask. Then, by etching, the conductive layer 28 a    which functions a heat radiating plate is formed just below the    conductive circuit (including via land) 28 and the IC chip (FIG.    6(B)).

In this treatment process, after photosensitive dry film resist isbonded to the surface of the copper foil, it is exposed to lightfollowing a predetermined circuit pattern and developed to form etchingresist. By etching metallic layer of a portion in which no etchingresist is formed, a conductive circuit pattern including the via land isformed.

As this etching solution, it is preferable to use at least one selectedfrom solutions including sulfuric acid—hydrogen peroxide, persulfate,cupric chloride, ferric chloride.

As pretreatment for forming the conductive circuit 28 by etching thecopper foil, it is permissible to etch the entire surface of the copperfoil so that preferably, the thickness thereof is 1-10 μm and morepreferably, 2-8 μm, in order to facilitate formation of a fine pattern.

Although the inside diameter of via land as part of the conductivecircuit is substantially the same as the diameter of the via hole andits outside diameter is preferred to be in a range of 50-250 μm.

-   (9) It is permissible to form thin film 29 of tin or the like on the    surface of the conductor circuit formed in the (8) by electroless    deposition (FIG. 6(C)).

For electroless deposition bathing to form tin contained plating film,tin borofluoride—thiourea solution or tin chloride—thiourea solution isused and a preferred plating condition is that the plating is carriedout for 1-5 minutes at temperatures of 20° C.-60° C.

According to the electroless plating treatment, copper-tin displacementreaction based on the metal complex formation of thiourea occurs on thesurface of the copper pattern and tin thin film layer is formed inthickness of 0.01-1 μm.

Roughing treatment is carried out to the surface of the conductorcircuit 28 formed in the step (7) as required and tin layer formed inthe step (8) can be formed on that roughed layer.

Further, instead of tin layer, it is preferable to cover with protectivefilm composed of at least one kind selected from zinc, nickel andphosphor or protective film composed of precious metal such as gold,platinum.

The purpose of the roughing treatment is to improve adhesion with theadhesive agent layer upon constructing into multi-layers to preventdelamination (delamination).

As the roughing treatment method, for example, soft etching treatment,blacking (oxidation)—reduction treatment, formation of needle-like alloyplating of copper-nickel-phosphorus (made by EBARA YUJIRAITO; productname, INTERPLATE) and surface roughing with etching solution named “MECETCH BOND” made by MEC are available.

The aforementioned roughed layer is preferred to be formed with etchingsolution and can be formed by etching the surface of a conductor circuitusing mixture water solution of cupric complex and organic acid. Suchetching solution is capable of dissolving a copper conductor circuitpattern under oxygen existing condition such as spray, bubbling and itis estimated that the reaction is advanced as follows.Cu+Cu(II)A_(n)→2Cu(I)A_(n/2)2Cu(I)A_(n/2) +n/4O₂ +nAH(aeration)→2Cu(II)A_(n) +n/2H₂Owhere A designates complexing agent (acts as chelating agent), ndesignates coordination number.

As indicated in the above equation, generated cuprous complex dissolvesby the action of acid and combines with oxygen to turn to cupriccomplex, thereby contributing to oxidation of copper. As the cupriccomplex used in the present invention, azoled cupric complex isrecommended. The etching solution composed of organic acid—cupriccomplex can be controlled by dissolving the azoled cupric complex andorganic acid (halogen ion as required) into water.

Such etching solution is formed of water solution in which for example,10 weight parts of imidazoled copper (II) complex, 7 weight parts ofglycol acid and 5 weight parts of potassium chloride.

Further, the single side circuit board B may be formed without roughingtreatment or formation of a covering layer.

-   (10) After releasing the protective film 25 from the surface of the    insulating base material 10 containing soldered bump, the surface of    the insulating base material is coated with the resin adhesive agent    32 (FIG. 6(D)).

The resin adhesive agent is applied to the entire surface containingsoldered bump of the insulating base material or the surface containingno soldered bump, so that adhesive agent layer composed of dried uncuredresin is formed. This adhesive agent layer is desired to be pre-cured tofacilitate its handling and its thickness is desired to be in a range of5-50 μm.

The adhesive agent layer is preferred to be composed of organic adhesiveagent and the organic adhesive agent is preferred to be at least oneresin selected from epoxy resin, polyimide resin, thermosettingpolyphenolene ether (PPE), composite resin of epoxy resin andthermoplastic resin, composite resin of epoxy resin and silicone resinand BT resin.

Coating with the uncured resin which is organic adhesive agent can becarried out using a curtain coater, spin coater, roll coater, spraycoater, screen printing or the like. Further, formation of the adhesiveagent can be carried out by laminating with adhesive agent sheet.

The single side circuit board B manufactured through the step (8)-(10)possesses a conductor circuit on a surface of the insulating basematerial 10 and the soldered bump 24 composed of solder plating on theother surface and further, the adhesive agent layer 26 for bonding toother insulating base material or the adhesive agent layer 32 forbonding to the copper foil is formed on the surface of the insulatingbase material containing the soldered bump 24.

-   (11) With the face on the conductive bump side of the single side    circuit board A facing downward, the single side circuit board B is    laid on that face in the same direction. The copper foil 30 5-18 μm    thick having a mat face having a surface roughness of 1.0 μm is laid    on the surface on the soldered bump 24 side of the single side    circuit board B (FIG. 7(A)) and pressed with heat at heating    temperature of 150-200 μC and under an applied pressure of 1-10 MPa    so as to integrate the single side circuit board A with the single    side circuit board B (FIG. 7(B)).

At this time, metal or resin film is nipped between the opening 10 a inthe single side circuit board A and a pressing plate. This is effectivefor preventing adhesive agent from flowing out and avoiding deflectionin position and unevenness in pressure at the time of pressing. In thiscase, it is permissible to put nothing or only place a pressureequalizing plate having a convex portion.

Preferably, such pressing with heat is carried out under a reducedatmospheric pressure and the uncured resin adhesive agent layer 26 ishardened so that the single side circuit board A and the single sidecircuit board B are bonded together. By hardening the adhesive agentlayer 32, the copper foil 30 is bonded.

-   (12) By etching the upper copper foil 12 and the lower copper foil    30 of the circuit boards integrated in the (11), the conductor    circuit 36 and the conductor circuit 38 (including the via hole land    and pad 36 p) are formed in the upper layer and the lower layer of    the multi-layer printed wiring board (see FIG. 7(C)).

In this treatment process, first, photosensitive dry film resist isbonded to the surface of the copper foil 12 and the copper foil 30 andafter that, exposed to light following a predetermined circuit patternand developed to form etching resist. By etching metallic layer at aportion in which no etching resist is formed, the conductor circuit 36and the conductor circuit 38 containing the via hole land are formed.

-   (13) Next, the solder resist layer 40 is formed on the outer sides    of the single side circuit boards A, B (FIG. 8(A)). In this case,    solder resist composition is applied to the entire outer surface of    each of the circuit boards A, B and after drying that applied film,    a photo mask film on which an opening is drawn is placed on this    applied film and exposed to light and developed to form the opening    44 which exposes the soldered pad portion located just above the    conductor circuit and via hole. Otherwise, it is permissible to bond    a film, expose to light and develop or make an opening with laser.-   (14) Before disposing a conductive bump, conductive ball or    conductive pin, which is an external terminal, on a soldered pad    (opening 44) exposed just above the via hole from an opening in the    solder resist obtained in the step (13), preferably, a metallic    layer composed of nickel 52—gold 54 is formed on each soldered pad    (FIG. 8(B)).

This nickel layer 52 is preferred to be 1-7 μm thick and the metalliclayer 54 is preferred to be 0.01-0.06 μm. The reason is that if thenickel layer is too thick, resistance is increased and if it is toothin, the nickel layer is likely to separate. Another reason is that ifthe metal layer is too thick, production cost is increased and if it istoo thin, adhesion effect with a soldered body drops. It is permissibleto form a single layer of tin or precious metal.

-   (15) Solder body is supplied onto metallic layer composed of    nickel-gold provided on the soldered pad portion so as to form    conductive bump as an external terminal by melting/solidification of    this solder body. Alternatively, conductive ball or conductive pin    is joined with the soldered pad portion to form a multi-layer    circuit board (FIG. 1(A)).

As a supply method for the solder body, it is permissible to use soldertransfer method or print method. According to this solder transfermethod, solder foil is bonded to a prepreg and by etching with thissolder foil left only at a portion corresponding to an opening portion,a solder pattern is formed as a solder carrier film. After coating asolder resist opening portion of a substrate with flux, this soldercarrier film is laid such that the solder pattern makes contact with thepad and by heating this, it is transferred.

On the other hand, according to the print method, with a print mask(metal mask) provided with an opening at a portion corresponding to thepad placed on a substrate, solder paste is printed and heat-treated. Assolder, it is permissible to use tin-silver, tin-indium, tin-zinc,tin-bismuth, tin-antimony. Their melting points are preferred to belower than the melting point of the conductive bump.

That is, appropriate solder body is supplied onto each solder padexposing from an opening in the solder-resist layer to form theconductive bump or connect the conductive ball or the conductive T-pin.

As the solder material for connecting the conductive ball 56 or theT-pin, it is preferable to use tin/antimony solder, tin/silver solder,tin/silver/copper solder each having a higher melting point than themelting point of the conductive bump.

According to the embodiment following the steps (1)-(15), in themulti-layer printed wiring board 60, the single side circuit board A andthe single side circuit board B are overlaid in the same direction andwith the copper foil 30 disposed such that its mat face opposes thesurface of the solder bump side of the single side circuit board B,pressed with heat to bond together the single side circuit boards whilethe copper foil 30 is pressed against the single side circuit board B,thereby forming the multi-layer structure. Then, by etching the copperfoil 12 on the single side circuit board A and the copper foil 30 on thesingle side circuit board B2, the conductor circuits 36, 38 are formed.In addition to such an embodiment, it is permissible to adopt themanufacturing process described in (1) modification 1 or (2)modification 2, later.

(1) Modification 1

With the mat face of the copper foil 30 opposing the surface on thesolder bump 24 side of the single side circuit board B (FIG. 9(A)), thecopper foil 30 is contact-bonded to the single side circuit board B byvacuum heating press (FIG. 9(B)). After that, by etching with theetching protective film attached, the copper foil is etched selectivelyso as to form the conductor circuit 38 having a predetermined pattern,thereby forming the double side circuit board B (FIG. 9(C)).

After that, with the face on the conductor circuit 28 side of thecircuit board B opposing the soldered bump 24 side of the single sidecircuit board A (FIG. 9(D)), they are pressed with heat under vacuum toform multi-layer structure (FIG. 9(E)). After that, by etching thecopper foil of the single side circuit board A, a conductor circuit isformed (see FIG. 7(C)).

(2) Modification 2

By etching the copper foil 12 of the single side circuit board A shownin FIG. 4(C), the conductor circuit 36 is formed (FIG. 10(A)) and anopening 10 a is made in the substrate 10 with a router or by punching(FIG. 10(B)). After that, with the double side circuit board B in whichthe conductor circuit 38 is formed in the step of FIG. 9(C), opposingthe single side circuit board A (FIG. 10(C)), they are pressed with heatunder vacuum to form the multi-layer structure (FIG. 10(D)).

Although according to the above-described embodiment, two layers areformed by integrating the two single side circuit boards, it is possibleto form multi-layer structure having a necessary number of layers byincreasing the quantity of the single side circuit boards even if it isthree or more.

Example 1

-   (1) First, a single side circuit board constituting a multi-layer    printed wiring board is produced. For this circuit board, a single    side copper stretched layered board obtained by overlaying a prepreg    as B stage in which epoxy resin is impregnated with glass cloth and    copper foil and then pressing them with heat is used as a starting    material.

This insulating base material is 75 μm thick and the copper foil is 18μm thick. The surface on an opposite side to the copper foil formingface of this layered board is laminated with PET film 12 μm thick andhaving adhesive agent layer 12 μm thick.

-   (2) Next, by irradiating the PET film with carbon dioxide laser, a    via hole forming opening going through the PET film and insulating    base material up to the copper foil is made and further it is    permissible to de-smear the inside of the opening by oxygen plasma    discharge or dipping in chemical solution of acid, oxidizing agent    or alkali. By the de-smear treatment, the base material is smoothed    and resin residue can be removed from the conductor portion, which    is the copper foil. As a result, even if conductive filler is    loaded, connectivity and reliability are secured. Although the resin    residue causes any problem, no problem occurs because it is removed.

According to this embodiment, to form an opening for via hole formation,a high peak short pulse oscillation carbon dioxide laser processingmachine made by MITSUBISHI ELECTROC was used. Glass cloth epoxy resinbase material 60 μm thick whose resin face is laminated entirely withPET film 22 μm thick, is irradiated with laser beam from the PET filmside according to mask imaging method to form openings for via holeformation 150 μm in diameter at a speed of 100 holes/second.

-   (3) With the PET film bonded to the copper foil face of the    insulating base material after de-smear treatment, electrolytic    copper plating with copper foil as plating lead was carried out to    fill the opening with electrolytic copper plating to form a via    hole. When the electrolytic copper plating is exposed slightly over    the top of the opening, it is permissible to remove the exposed    portion for flattening by sander belt polishing and buffing.    [Water Solution for Electrolytic Copper Plating]-   sulfuric acid: 175 g/l-   cupric sulfate: 78 g/l-   additive (made by ATOTECH JAPAN, product name: KAPARASIDO GL)    [Electrolytic Plating Condition]-   Current density: 6 A/dm²-   Time: 60 min.-   Temperature: 25° C.    (4) Further, by executing electrolytic solder plating under a    following condition, solder plating layer is formed on copper    plating layer filled in the opening and soldered bump projecting by    3-10 μm form the surface of the insulating base material is formed.    [Electrolytic Solder Plating Solution]-   Metal composition ratio: formed in a range of Sn/Cu=99.9/0.1-70/30-   Additive: 5 ml/l    (Electrolytic Solder Plating Condition)-   Temperature: 21° C.-   Current density: 0.41 A/dm²-   As its specific example, Sn/Cu=99.3/0.7 (melting point 227° C.),    Sn/Cu=95/5 (melting point: 310)    In this case, formed soldered bump whose ratio was    Sn/Cu=99.9/0.1-90/10 is taken as an optimum example and a case of    Sn/Cu>90/10 was taken as an application example.-   (5) Next, after the PET film bonded to the insulating base material    in the (3) was released, the entire surface on the soldered bump    side of the insulating base material was coated with epoxy resin    adhesive agent and pre-cured to form adhesive agent layer for    multi-layer structure.-   (6) An opening was made in the insulating base material formed in    the step (5) with router or by punching or laser. The area for the    opening was 15-70%. According to this embodiment, the opening area    was 36.5%.

The single side circuit board A produced in the steps (1)-(6) is acircuit board to be disposed as an upper layer upon constructing into amulti-layer structure, and the inside of the opening is an area in whichthe IC chip is mounted.

-   (7) After the same treatment as the steps (1)-(4) was carried out,    the PET film was released from the copper foil bonding surface of    the insulating base material and with the etching protective film    bonded to the surface on the soldered bump side of the insulating    base material, appropriate etching was carried out to the copper    foil to form a conductor circuit having a predetermined pattern.    It is permissible to carry out electroless plating on the surface of    the conductor circuit obtained in the step (7) using tin    borofluoride—thiourea solution as electroless plating bath under a    plating condition around 45° C. for about five minutes to form thin    tin layer 0.1 μm thick.-   (8) After the etching protective film bonded to the insulating base    material was released in the step (6), epoxy resin adhesive agent    was applied to the entire surface on the soldered bump side of the    insulating base material and pre-cured to form adhesive agent layer    for forming multi-layer structure by bonding together the circuit    boards.

The single side circuit board A manufactured following the steps (6)-(8)is a board to be combined with the single side circuit board B.

-   (9) After the single side circuit board B on which the copper foil    30 having a mat face was subjected to the same treatment as the    steps (1)-(5) and (7), epoxy resin adhesive agent was applied to    bond the copper foil 30 having the mat face on the insulating base    material 10 effectively instead of the adhesive agent of the    step (8) and dried at 60° C. for 30 minutes to form a resin adhesive    agent layer 20 μm thick.-   (10) After the single side circuit board A produced following the    steps (1)-(8) and the single side circuit board B produced following    the step (9) were overlaid in the same direction, a copper foil 12    μm thick whose single side was subjected to mat processing, having a    surface roughness of 1.0 μm was heat-pressed to the face on the    soldered bump side of the single side circuit board B such that the    mat face opposed, under a condition of heating temperature of 200°    C., heating time of 10 minutes, pressure of 2 MPa, and degree of    vacuum of 2.5×10³ Pa, so that the respective single side circuit    boards A, B were bonded together and then, the copper foil was    bonded to the single side circuit board to form the multi-layer    structure.-   (11) After that, a conductor circuit (including via land) was formed    on the copper foils of the single side circuit board A and single    side circuit board B of the multi-layered board by appropriate    etching treatment.-   (12) Before forming solder-resist layer on the surface of the    multi-layer board produced following the steps (1)-(11), it is    permissible to provide a roughed layer of copper—nickel—phosphorus    or a roughed face by etching as required.-   (13) On the other hand, 46.67 weight part of oligomer (4,000 in    molecular weight) provided with photo sensitivity in which the epoxy    base 50% of 60 weight % cresol-novolac type epoxy resin (made by    NIPPON KAYAKU) dissolved in DMDG was made acrylic, 14.121 weight    part of 80 weight % bisphenol A type epoxy resin (made by YUKA    SHELL, Epikote 1001) dissolved in methyl ethyl ketone, 1.6 weight    part of imidazole hardening agent (made by SHIKOKU CORP., 2E4MZ-CN),    1.5 weight part of polyacryl monomer (made by NIPPON KAYAKU, R604),    which is photo sensitive monomer, 30 weight part of polyacryl    monomer (made KYOEISHA CHEMICAL, DPE6A), and 0.36 weight part of    leveling agent (made by KYOEISHA, Polyflow No. 75) composed of acryl    ester polymer were mixed and then, 20 weight part of benzophenone as    photo initiator (KANTO CHEMICAL) and 0.2 weight part of EAB (made by    HODOGAYA CHEMICAL) as photosensitizer were added to this mixture and    further, 10 weight part of DMDG (di-ethylene glycol di-methyl ether)    was added, so that solder resist composition whose viscosity was    adjusted to 4±0.3 Pa·S at 25° C. was obtained.

As for measurement of the viscosity, if the B type viscosimeter (made byTOKYO KEIKI, DVL-B type) was 60 rpm, rotor No. 4 was used and if it was6 rpm, rotor No. 3 was used.

-   (14) The solder resist composition obtained in the step (13) was    applied to the surface of the multi-layer circuit board obtained in    the step (11) in the thickness of 20 μm.

Next, after the drying treatment was carried out at 70° C. for 20minutes and at 100° C. for 30 minutes, the side in which chrome layerwas formed of a soda lime glass substrate 5 mm thick on which a circularpattern (mask pattern) of solder resist opening portion was drawn withchrome layer was fitted to the solder—resist layer and exposed to lightwith 1000 mJ/cm² ultraviolet ray and subjected to DMTG developmenttreatment. Further, the heat treatment was carried out at 80° C. for anhour, at 100° C. for an hour, at 120° C. for an hour and at 150° C. forthree hours to form solder-resist layer (20 μm thick) having an opening(200 μm in opening diameter) corresponding to a pad portion.

-   (15) Next, a substrate in which solder-resist layer was formed was    dipped in electroless nickel plating solution having pH=5 composed    of nickel chloride of 30 g/1, sodium hypophosphite of 10 g/1, sodium    citrate of 10 g/1 for 20 minutes, so that nickel plating layer 5 μm    thick was formed on the opening portion.

That substrate was dipped in electroless gold plating solution composedof gold potassium cyanide of 2 g/1, ammonium chloride of 75 g/1, sodiumcitrate of 50 g/1, and sodium hypophosphite of 10 g/1 at 93° C. for 23seconds to form gold plating layer 0.03 μm thick on the nickel platinglayer, so that covering metallic layer composed of nickel plating layerand gold plating layer was formed. Depending on a case, it ispermissible to form a single layer of tin or precious metal.

-   (16) Then, solder paste composed of tin/silver solder having a    melting point of about 190° C. was printed on solder pad exposed    from an opening of solder resist layer covering the single side    circuit board A located as an upper layer and by reflowing at 220°    C., solder balls were connected on both sides to form a multi-layer    printed wiring board.    [Modification 1 of Example 1]

Although the multi-layer printed wiring board of the modification 1 ofthe example 1 had the same structure as the example 1 (the via holes 18were kept deflected between upper and lower single side boards and theBGA 56 was kept deflected from just below), the conductive bump wasformed of Sn/Zn (97:3).

[Modification 2 of Example 1]

Although the multi-layer printed wiring board of the modification 2 ofthe example 1 had the same structure as the example 1, the conductivebump was formed of Sn/Sb (95:5).

[Modification 3 of Example 1]

Although the multi-layer printed wiring board of the modification 3 ofthe example 1 had the same structure as the example 1, the conductivebump was formed of Sn/Pb (97:3).

[Modification 4 of Example 1]

Although the multi-layer printed wiring board of the modification 4 ofthe example 1 had the same structure as the example 1, the conductivebump was formed of Sn/Ag (95:5).

[Change 1 of Example 1]

In the multi-layer printed wiring board of the change 1 of the example1, its conductive bump was formed of Sn/Su (97:3). Different from thestructure of the example 1, as shown in FIG. 14(A), the externalterminal 56 was disposed on the rear face just below the externalterminal 56 on the front face.

[Change 2 of Example 1]

In the mulit-layer printed wiring board of the change 1 of the example1, its conductive bump was formed of Sn/Su (97:3). However, differentfrom the structure of the example 1, as shown in FIG. 14(B), the viahole 18 in the upper single side circuit board was disposed just abovethe via hole 18 in the lower single side circuit board.

[Change 3 of Example 1]

In the multi-layer printed wiring board of the change 1 of the example1, its conductive bump was formed of Sn/Su (97:3). Different from thestructure of the example 1, as shown in FIG. 14(C), the externalterminal 56 on the rear face was disposed just below the externalterminal 56 on the front face and the via hole 18 in the upper singleside circuit board was disposed just above the via hole 18 in the lowersingle side circuit board.

Comparative Example 1

As shown in FIG. 15(A), a multi-layer printed wiring board was formed ofa single side circuit board according to the manufacturing methoddescribed in Japanese Patent Application Laid-Open No. HEI10-13028. FIG.15(B) shows a condition in which the multi-layer printed wiring boardshown in FIG. 15(A) is mounted on a daughter board 90. FIG. 15(C) showsa condition in which IC chips 70A, 70B are stacked. Here, the via holes118 are constructed by filling non-through holes with conductive pasteand the single side circuit boards are overlaid without use of anyconductive bump. The via holes 118 are arranged such that they arestacked. A land 136 is formed by extending a conductor circuit connectedto the via hole and a wire pad of the IC chip 70 is connected to theland 136 with wire 72.

Comparative Example 2

Although the multi-layer printed wiring board of the comparative example2 has the same structure as the comparative example 1, the non-throughholes are filled with plating instead of conductive paste.

[Comparison Test]

According to this example, a PKG substrate loaded with an IC chip wasconnected to the top face of the board and a multi-layer substrateproduced according to subtractive method loaded with only electroniccomponents such as capacitor was connected to the bottom face of theboard.

According to the comparative example, an IC chip structured intomulti-layer structure by stacking layers was loaded on the top face ofthe board and the side in which the BGA was disposed was connected to amulti-layer board (daughter board 90) produced according to thesubtractive method loaded with only electronic components such ascapacitor.

FIG. 16 shows whether or not the IC chip is checked about five piecescreated according to the example 1 and the comparative examples 1, 2,whether or not repair is enabled (whether or not the IC chip wasreplaced), and result of conductivity test performed as reliability test(with three minutes at 135° C. to three minutes at −65° C. as a cycleunder heat cycle condition, performed 500 cycles, 1000 cycles, 2000cycles and 3000 cycles).

It was verified that electric connectivity and reliability were securedas compared with a conventional case (comparative example).

Upon comparison of the example 1, it was verified that a structure notadopting the stacked structure (disposing a via hole just above a viahole), in which an external terminal is deflected from just below anexternal terminal on an opposite face, was the most excellent in termsof electric connectivity and reliability. Contrary to this, an exampleadopting the stacked structure in which the external terminals waslocated at the same position deteriorated early. This was indicated tobe of a structure in which generated stress was hard to relax.

Further, it was verified that an example in which Cu, Zn, Sb was mixedin its conductive bump had a higher reliability than other conductivemetals.

Because the example 1 possesses a pad for connecting an externalterminal on both faces of the multi-layer printed wiring board, otherprinted wiring board can be connected to the both faces. As a result,freedom of pulling out a wire is intensified and a structure whichenables the IC chip to be multi-layered is obtained.

Further, by using the conductive bump, the reliability can be improved.Mixing of Cu, Zn and Sb can contribute to improvement of thereliability.

Because the via holes are not stacked and when external terminals areprovided on both faces, the external terminal is not provided on anopposite face just below another external terminal, the reliability canbe improved.

Second Embodiment

First, the structure of a multi-layer printed wiring board produced byoverlaying the single side circuit boards, according to the secondembodiment of the present invention will be described with reference toFIGS. 17, 18.

FIG. 17(A) shows a multi-layer printed wiring board 100 constituting apackage board and FIG. 17(B) shows a condition in which the IC chip 70is mounted on the multi-layer printed wiring board 100. FIG. 18(A) showsa condition in which the IC chip 70 of the multi-layer printed wiringboard shown in FIG. 17(A) is molded with resin and FIG. 18(B) shows acondition in which the IC module 120 is mounted on the multi-layerprinted wiring board 100 loaded with the IC chip 70.

As shown in FIG. 17(A), the multi-layer printed wiring board 100comprises two layers, the single side circuit board A and the singleside circuit board B. The top face of the single side circuit board Aand the bottom face of the single side circuit board B are covered withsolder resist layer 40. An opening (bored portion) 10 a foraccommodating an IC chip is formed in the center of the upper singleside circuit board A. A conductor circuit 36 and bonding pad 36 a areformed on the top face of the single side circuit board A. A BGA 56 forconnecting to the IC module is disposed on an opening 44 in the solderresist layer 40 on the conductor circuit 36. Further, a via hole 18 isformed in an opening 16 going through an insulating base material 10under the conductor circuit 36 and the bonding pad 36 p. A soldered bump24 for connecting to a conductor circuit 28 of the lower single sidecircuit board B is disposed on the bottom end of the via hole 18. Thesingle side circuit board A and the lower single side circuit board Bare connected through adhesive agent layer 26. A metallic layer 28 a isprovided in the center of the top face of the lower single side circuitboard B to radiate heat of the IC chip 70. A heat radiating via hole 18a is provided below the metallic layer 28 a. The via hole 18 forconnecting a circuit is provided below the conductor circuit 28 on thetop face of the lower single side circuit board B. A conductor circuit38 is connected to the soldered bump 24 of the lower single side circuitboard B and the BGA 56 is attached to the conductor circuit 38. FIG.19(B) shows a plan view of FIG. 17(B) and FIG. 19(A) shows a conditionbefore formation of the solder resist layer of the multi-layer printedwiring board shown in FIG. 17(B). As shown in FIG. 19(A), the conductorcircuit 36 just above the via hole 18 is formed circularly and thebonding pad 36 p connected directly to the via hole 18 is formedrectangular. As shown in FIG. 19(B), the bonding pad 36 p is exposedpartially through an elliptic opening 44 a in the solder resist layer40. Although according to the second embodiment, the opening 44 a isformed elliptically, this shape may be circular, oval shape, polygonal,or a square which exposes front ends of all the bonding pads 36 as shownin FIG. 20(B).

An IC chip 70 is accommodated within the opening 10 a in the multi-layerprinted wiring board 100 and on the metallic layer 28 a as shown in FIG.17(B). The IC chip 70 is connected to the bonding pad 36 p under theopening 44 a in the solder resist layer 40 on the multi-layer printedwiring board side with wire 72. FIG. 20(A) shows a plan view of FIG.17(B).

As shown in FIG. 18(A), the IC chip 70 and the opening 10 a are moldedwith resin 74.

As shown in FIG. 18(B), the BGA 56 on the front face of the multi-layerprinted wiring board 100 is connected to the IC module 120 through aterminal 132. On the other hand, the BGA 56 on the rear face of themulti-layer printed wiring board is connected to a printed wiring boardor the like (not shown). In the IC module 120, an IC chip 122 placed ona terminal plate 130 is molded with resin 124 and the IC chip 122 and aterminal 132 of the terminal plate 130 are bonding-connected with a wire128.

In the multi-layer printed wiring board 100 of the second embodiment,the bonding pad 36 p is connected directly to the via hole 18 ofconductive material filled in the non-through hole. That is, by fillingthe non-through hole leading to the conductor circuit (bonding pad) 36 pwith conductive material, different from the conventional technologydescribed with reference to FIG. 24, the conductive material (via hole)and the conductor circuit (bonding pad) can be connected not through thevia hole land because the conductive circuit (bonding pad) 36 p isconnected with the conductive material (via hole) 18. Because any viahole land having a diameter larger than the width of wire of bonding padis not used, wiring density can be intensified.

Because the BGAs 56 are disposed on the front face and rear face of themulti-layer printed wiring board 100 of the second embodiment, otherprinted wiring board can be connected to its both sides. For example,with an IC module 120 mounted through the BGA 56 on the front face, itcan be connected to a printed wiring board through the BGA 56 on therear face. Further, freedom of the shape of an IC module to be mountedis intensified.

According to the second embodiment, the BGA 56 of the rear face isdisposed just below the BGA 56 and the pad 36 p of the front face suchthat it does not overlap. That is, as shown in FIG. 18, the center lineX1 of the via hole 18 on which the BGA 56 is to be mounted is deflectedfrom the center line X2 of the via hole 18 on which the BGA 56 is to bemounted. As a consequence, the same effect as the first embodiment canbe obtained.

According to the second embodiment, the IC chip 122 is a memory having asmall heat release value and the IC chip 70 is a logic IC having a largeheat release value. The metallic layer 28 a is provided just below thisIC chip 70 and the metallic layer 58 a is connected to the BGA 56through the via hole 18 a. With this structure, heat can be transmittedto a printed wiring board connected to the BGA 56 efficiently to radiatethe heat.

The multi-layer printed wiring board according to modification of thesecond embodiment can be constructed like the modifications of the firstembodiment described with reference to FIGS. 11, 12.

Because the manufacturing method of the multi-layer printed wiring boardaccording to the second embodiment of the present invention is the sameas the first embodiment, description thereof is omitted. In themeantime, as modifications 1, 2 of the manufacturing method of thesecond embodiment, the same configuration as the modification 1 (FIG.11) and modification 2 (FIG. 12) of the manufacturing method of thefirst embodiment can be adopted.

Third Embodiment

Subsequently, a multi-layer printed wiring board according to the thirdembodiment of the present invention will be described with reference toFIGS. 21, 22.

FIG. 21(A) shows a section of the multi-layer printed wiring boardaccording to the third embodiment and FIG. 21(B) shows a condition inwhich an IC chip is mounted on the multi-layer printed wiring board.FIG. 22(A) is a plan view of the multi-layer printed wiring board ofFIG. 21(A) and FIG. 22(B) is a plan view of the multi-layer printedwiring board of FIG. 21(B).

According to the second embodiment described with reference to FIGS. 17,19, the bonding pad 36 p is formed rectangular and the via hole 18 isconnected to an end of the bonding pad 36 p while wire 72 is bonded tothe other end, according to the third embodiment, a circular bonding pad36 p is disposed just above the via hole 18 and the wire 72 is bonded.

Because the multi-layer printed wiring board according to the thirdembodiment, the bonding pad 36 p is disposed just above the via hole 18composed of conductive material filled in a non-through hole, anecessity of disposing around the bonding pads is eliminated andconsequently, wiring density can be raised. Although according to thethird embodiment, the bonding pad is formed circularly, this shape maybe elliptic, oval, polygonal and of other shape.

Example 2

Because the manufacturing method of the example 2 is the same as theabove-described example 1, description thereof is omitted.

[Modification 1 of Example 2]

Although the mulit-layer printed wiring board according to themodification 1 of the example 2 had the same structure as the example 2(the via holes 18 are deflected between the upper and lower single sidecircuit boards and the BGA 56 is deflected from just below), theconductive bump is formed of Sn/Zn (97:3).

[Modification 2 of Example 2]

Although the multi-layer printed wiring board of the modification 2 ofthe example 2 had the same structure as the above-described example 2,the conductive bump was formed of Sn/Sb (95:5).

[Modification 3 of Example 2]

Although the multi-layer printed wiring board of the modification 3 ofthe example 2 had the same structure as the above-described example 2,the conductive bump was formed of Sn/Pb (97:3).

[Modification 4 of Example 2]

Although the multi-layer printed wiring board of the modification 4 ofthe example 2 had the same structure as the above-described example 2,the conductive bump was formed of Sn/Ag (95:5).

[Change 1 of Example 2]

In the multi-layer printed wiring board of the change 1 of the example2, the conductive bump was formed of Sn/Su (97:3). However, differentfrom the structure of the example 2, as shown in FIG. 14(A), theexternal terminal 56 was disposed on the rear face just below theexternal terminal 56 on the front face.

[Change 2 of Example 2]

The multi-layer printed wiring board of the change 1 of the example 2was formed of Sn/Su (97:3). However, different from the structure of theexample 2, as shown in FIG. 14(B), the via hole 18 in the upper singleside circuit board was disposed just above the via hole 18 in the lowersingle side circuit board.

[Change 3 of Example 2]

In the multi-layer printed wiring board of the change 1 of the example2, the conductive bump was formed of Sn/Su (97:3). However, differentfrom the structure of the example 2, as shown in FIG. 14(C), theexternal terminal 56 on the rear face was disposed just below theexternal terminal 56 on the front face and the via hole 18 in the uppersingle side circuit board was disposed just above the via hole 18 in thelower single side circuit board.

Comparative Example 3

As shown in FIG. 15(A), a multi-layer printed wiring board wasconstructed with a single side circuit board according to themanufacturing method described in Japanese Patent Application Laid-OpenNo. HEI10-13028. FIG. 15(B) shows a condition in which the multi-layerprinted wiring board shown in FIG. 15(A) is mounted on the DOTA board90. FIG. 15(C) shows a condition in which the IC chips 70A, 70B arestacked. Here, the via holes 118 were constructed by filling thenon-through holes with conductive paste and the single side circuitboards were overlaid without using any conductive bump. The via holes118 were disposed such that they are stacked. A land 136 was formed byextending a conductor circuit connected to the via hole and a wiring padof the IC chip 70 was connected with the land 136 with wire 72.

Comparative Example 4

Although the multi-layer printed wiring board of the comparative example4 had the same structure as the comparative example 3, the non-throughholes were filled with plating instead of conductive paste.

[Comparison Test]

According to the example 2, a PKG substrate loaded with an IC chip wasconnected to the top face of the board and a multi-layer substrateproduced according to subtractive method loaded with only electroniccomponents such as capacitor was connected to the bottom face of theboard.

According to the comparative examples 3, 4, an IC chip structured intomulti-layer structure by stacking layers was loaded on the top face ofthe board and the side in which the BGA was disposed was connected to amulti-layer board (daughter board 90) produced according to thesubtractive method loaded with only electronic components such ascapacitor.

FIG. 23 shows an average value as a result of measuring inductance offive pieces produced in the example 1 and comparative examples 3, 4 in asimple manner. The measurement result is a simulation result. At thesame time, it shows a result of conductivity test performed asreliability test (with three minutes at 135° C. to three minutes at −65°C. as a cycle under heat cycle condition, performed 500 cycles, 1000cycles, 2000 cycles, 3000 cycles).

It was verified that the inductance could be reduced and electriccharacteristic and reliability were secured as compared with theconventional example (comparative example). Further, it was verifiedthat an example in which Cu, Zn, Sb was mixed in its conductive bump hada higher reliability than other conductive metals. Further, it wasverified that a structure not adopting the stacked structure (via holesare disposed just above the via holes) and in which the externalterminal was deflected from just below the external terminal on anopposite face had more excellent electric connectivity and reliability.

In the structure of the comparative example having no conductive bump,its reliability drops because peeling of a bonding face occurs early.

According to the example, dead space can be reduced. Thus, as comparedwith the configuration of the comparative example, its size can bereduced by 5-10% even if an IC having the same clock number isinstalled.

The reason is that the dead space (area in which substantially wiringcannot be placed) in the vicinity of the wiring pad of the IC paddecreases.

Because according to the example 2, the wire is connected to theconductor circuit on the via hole in which the non-through hole isfilled with conductive material, the dead space for wiring decreasesthereby reducing the size of the configuration.

Further, improvement of electric characteristic, for example, reductionof inductance is achieved.

Additionally, reliability is improved because the conductive bump isused. If the via holes are not formed into the stacked structure or theexternal terminals are provided on both sides, the reliability can beimproved by not providing the external terminal of an opposite face justbelow the external terminal.

1. A multi-layer printed wiring board comprising: a first substratehaving an opening and having a plurality of external terminalspositioned to be connected to a package substrate; a second substratelaminated to the first substrate and having a plurality of externalterminals positioned to be connected to a mother board, the secondsubstrate having a continuous metallic layer portion in the opening ofthe first substrate and a plurality of non-through holes filled withconductive material and connected to the continuous metallic layerportion such that the non-through holes are electrically connected toeach other; and an IC component having a terminal side including aplurality of terminals, and a non-terminal side which is opposite to theterminal side, the IC component being loaded in the opening of the firstsubstrate such that the non-terminal side of the IC component contactsthe metallic layer portion and the terminals of the IC component faceoutward of the opening in the first substrate, wherein the IC componentis accommodated in the opening such that the metallic layer portion andnon-through holes of the second substrate irradiate heat generated bythe IC component.
 2. The multi-layer printed wiring board according toclaim 1, wherein the external terminals of the first substrate aredisposed offset the external terminals of the second substrate.
 3. Themulti-layer printed wiring board according to claim 1, furthercomprising a plurality of conductive non-through holes provided in thefirst substrate and connected to the external terminals of the firstsubstrate and a plurality of conductive non-through holes provided inthe second substrate and connected to the external terminals of thesecond substrate, wherein the conductive non-through holes in the firstsubstrate and the conductive non-through holes in the second substrateare positioned offset from each other.
 4. The multi-layer printed wiringboard according to claims 1, further comprising a plurality of bondingpads provided for wire bonding the IC component in the first substrate.5. The multi-layer printed wiring board according to claim 1, whereinthe external terminals of the first substrate are positioned in aperipheral form surrounding the IC component, and the external terminalsof the second substrate are positioned in a grid form.
 6. Themulti-layer printed wiring board according to claim 1, wherein the ICcomponent has a bottom portion of which an entire surface of the bottomportion of the IC component is loaded over the metallic layer portion inthe second substrate.
 7. The multi-layer printed wiring board accordingto claim 1, wherein the first substrate has a plurality of terminalspositioned to be connected to the plurality of terminals of the ICcomponent, and the external terminals and terminals in the firstsubstrate are positioned to face the opposite side of the metallic layerportion of the second substrate.
 8. The multi-layer printed wiring boardaccording to claim 3, wherein the conductive non-through holes in thefirst and second substrates are provided with a plurality of conductivebumps, respectively.
 9. The multi-layer printed wiring board accordingto claim 4, wherein the plurality of bonding pads are connected to aplurality of conductive non-through holes formed underneath theplurality of bonding pads, respectively.
 10. The multi-layer printedwiring board according to claim 4, wherein the bonding pads have arectangular shape.
 11. The multi-layer printed wiring board according toclaim 9, wherein the plurality of conductive non-through holes formedunderneath the plurality of bonding pads, respectively, has a pluralityof conductive bumps, respectively, on an opposite face of the bondingpads.